1. Field of the Invention
The present invention relates to a chip package and a method for manufacturing the same. More particularly, it relates to a chip package of the type that has an interconnection pattern and ball pads formed by etching a metal layer on one side or both sides of a resin substrate, which includes a package such as a BGA package or a flip chip package and is mainly used as a package for mounting a chip such as an LSI chip, and a method for manufacturing the same.
2. Description of the Relevant Art
Recently, a BGA (Ball Grid Array), a flip chip package and the like which can be made to have more terminals have attracted attention since a semiconductor apparatus is requested to have a higher density and a higher speed. The BGA is most suitable for packaging of ICs such as a microprocessor and an ASIC which are required to have more terminals, and has the following characteristics.
(a) Since balls are arranged in a plane, it is possible to have more terminals by far than packaging technologies using a lead frame such as a QFP (Quad Flat Package), and it is also possible to have still more terminals than a PGA (Pin Grid Array).
(b) Since it has a larger lead pitch than the QFP, the precision of a mounter or the like is not always required to be high, and so the packaging yield is improved.
(c) The cost is relatively low.
(d) The heat dissipation property is excellent, so that the impedance can be low.
Until recently, attention had been paid to a ceramic BGA among BGAs from the viewpoint of reliability, but the priority is moving to plastic array packages from the viewpoint of cost reduction. In the plastic array packages of this kind, there are PBGA (Plastic BGA), TBGA (Tape BGA), xcexc-BGA, CSP (Chip Size Package, Chip Scale Package) and the like in a broader sense.
An example of the PBGA is shown in FIG. 1. On the IC chip 11 mounting surface of a resin substrate 12, an interconnection pattern 13 is formed, while on the other surface thereof, a large number of ball pads 14 are formed. These ball pads 14 and the interconnection pattern 13 are connected through through holes 16 for interconnection. The bottom surface of the IC chip 11 is connected to the ball pads 14 through through holes 17 for heat dissipation. On the ball pads 14, solder balls 15 are deposited. The interconnection pattern 13 is connected to pads formed on the IC chip 11 (not shown) through bonding pads 13a and wire bonders 18. The portion which includes the IC chip 11, the wire bonders 18, and the majority of the interconnection pattern 13 is covered with a mold resin 19.
Ordinarily, the bonding pads 13a and the ball pads 14 are Ni/Au plated (not shown) in order to improve the bonding property and the deposition property of the solder balls 15, and for that purpose the interconnection for electroplating is formed as shown in FIG. 2, for example. Each of the bonding pads 13a and ball pads 14 is connected to a tie bar 21 through a lead for plating 20. After the plating is finished, each device is made by cutting on cutting lines 22. The portion which need not be plated is previously covered with a solder mask 23 before the plating treatment.
An example of a BGA with a heat spreader is shown in FIGS. 3 and 4. BT (Bismaleimide Triazine) is used for forming a tape-shaped thin resin substrate 32. Since the BT resin has almost the same thermal transformation temperature (300xc2x0 C.) as a polyimide resin and has better adhesiveness to a copper foil and workability than the polyimide resin, it is used widely for LSI packages. On the bottom surface of the resin substrate 32, an interconnection pattern (not shown) and ball pads 34 are formed by etching a copper foil. On the ball pads 34, solder balls 15 are deposited. Onto the top surface of the resin substrate 32, a Cu ring 33 having a cavity 35 to accommodate an IC chip 11 is adhered. Onto the top surface of the Cu ring 33, a Cu heat spreader 38 is further adhered through an adhesive sheet 38a. In the center portion of the resin substrate 32, a dam 36 is formed so as to surround the cavity 35. After connecting wire bonders 18, an injection mold resin 39 is injected into the cavity 35 to be solidified. The ball pads 34 and bonding pads (not shown) comprise a Cu layer 34a and a Ni/Au layer 34b as shown in FIG. 4. A solder mask 43 is formed around the Ni/Au layer 34b. 
In the BGA with a heat spreader of the type shown in FIG. 3, since it is difficult to arrange the leads for plating 20 shown in FIG. 2 from the viewpoint of space, the Ni/Au layer 34b is formed by electroless plating. The leads for plating 20 and tie bars 21 shown in FIG. 2 are not formed during the manufacturing process.
An example of a conventional flip chip package wherein a semiconductor component is mounted by flip chip bonding is shown in FIGS. 5 and 6. On the chip 11 mounting surface of a resin substrate 12, an interconnection pattern 13 and ball pads 14a are formed, while on the other surface thereof, a large number of ball pads 14b are formed. These ball pads 14b and the interconnection pattern 13 are connected through through holes 16 for interconnection. The ball pads 14a under the chip 11 are connected to the ball pads 14b through through holes 17 for heat dissipation. On the ball pads 14b, solder balls 15 are deposited. The interconnection pattern 13 is connected to the chip 11 through the solder balls 15 deposited on the ball pads 14a. The space between the chip 11 and the resin substrate 12 is charged with a mold resin 19. On the portion of the interconnection pattern 13 except the ball pads 14a and 14b, a solder mask 23 is formed. The ball pads 14a and 14b comprise a Cu layer 34a and a Ni/Au layer 34b as shown in FIG. 6 and the solder mask 23 is formed around the Ni/Au layer 34b. 
The Ni/Au layer 34b in the flip chip package shown in FIGS. 5 and 6 is formed not by electroplating but by electroless plating. This is because flip chip packages tend to have high-density interconnections, and so it is difficult to form leads for electroplating between the high-density interconnections.
In the PBGA of the type shown in FIGS. 1 and 2, a large number of leads for plating 20 connected to each bonding pad 13a or ball pad 14 and tie bars 21 must be formed for electroplating, which prevents the interconnection pattern 13 and ball pads 14 from having a higher density. The leads for plating 20 inside the cutting lines 22 are left even after plating, leading to a possibility that they become a source of reflected noise, which adversely affects the electrical properties.
On the other hand, since the electroless plating is conducted in the BGA with a heat spreader of the type shown in FIGS. 3 and 4, the leads for plating 20 and the tie bars 21 need not be formed, and so there is no problem with increasing density of the interconnections and the like. However, the adhesive strength of the solder balls 15 to the ball pads 34 is low, so that the adhesion tends to be unstable.
Since the electroless plating is conducted in the flip chip package of the type shown in FIGS. 5 and 6 in the same manner as in the BGA with a heat spreader of the type shown in FIGS. 3 and 4, the leads for plating 20 and the tie bars 21 need not be formed and so there is no problem with increasing density of interconnections and the like. However, the adhesive strength of the solder balls 15 to the ball pads 14a and 14b is low, so that the adhesion tends to be unstable.
The present invention was developed in order to solve the above problems. It is an object of the present invention to provide a chip package wherein leads for plating need not be formed so as to enable the realization of higher density and an improvement of electrical properties while the plating is conducted by electroplating so that the adhesive strength of solder balls to pads is secured, and a method for manufacturing the same.
In order to achieve the above object, a chip package (1), according to the present invention has an interconnection pattern and ball pads formed by etching a metal layer on one side or both sides of a resin substrate, and is characterized by the surface of the interconnection pattern and ball pads which is coated with Ni and Au films by electroplating, and no leads for electroplating are formed since an electric current is applied to the metal layer during electroplating.
In the chip package (1), since an electric current is applied to the metal layer during electroplating, the leads for electroplating usually required are not needed. As a result, it is possible to inhibit the leads from preventing the density increasing and from deteriorating the electrical properties. Since the plating for forming the Ni and Au films is conducted by electroplating, a sufficient value of adhesive strength of the solder balls can be obtained.
A chip package (2) according to the present invention is characterized by the metal layer which includes a copper foil and an electroless copper plating layer in the chip package (1).
In the chip package (2), an adequate thickness of the metal layer can be secured, the copper foil has an excellent adhesiveness to the resin substrate and strength, and a large current can be passed through the copper foil during the formation of the Ni and Au films by electroplating.
A chip package (3) according to the present invention is characterized by the metal layer which includes an electroless copper plating layer in the chip package (1).
In the chip package (3), the metal layer comprising the electroless copper plating layer can be formed to be thin, i.e. 1 micron or so. As a result, the subsequent etching in patterning becomes easy and the quantity of overhang during etching is as small as possible, and so the interconnection pattern can easily have a higher density.
A chip package (4) according to the present invention is characterized by through holes formed in the resin substrate, having side walls which are coated with Ni and Au films by electroplating in one of the chip packages (1)-(3).
Conventionally, only Cu plating is conducted on the side walls of the through holes, not Ni/Au plating. But in the chip package (4), since the Ni/Au plating film is formed by electroplating, not only on the surface of the interconnection pattern and ball pads but also on the side walls of the through holes, the reliability of the chip package can be improved.
A method for manufacturing a chip package (1) according to the present invention includes the steps of:
forming a plating resist pattern on the surface of a metal layer formed on one side or both sides of a resin substrate;
applying an electric current to the metal layer to form Ni and Au films by electroplating on the metal layer surface which is not covered with the plating resist pattern; and
removing the plating resist pattern to etch the metal layer using the Ni/Au film as an etching mask.
In the method for manufacturing a chip package (1), since the Ni/Au film is formed by electroplating on the portion of the metal layer surface which is not covered with the plating resist pattern, then the metal layer used for the passage of electric current is etched using the Ni/Au film as an etching mask. Therefore, the interconnection pattern and ball pads made of the metal layer/Ni/Au film can be formed without forming leads for electroplating only if the metal layer surface except a portion to be an interconnection pattern and ball pads, is covered with the plating resist pattern. Furthermore, since the Ni/Au film is formed by electroplating, it has sufficient adhesive strength to the solder balls.
A method for manufacturing a chip package (2) according to the present invention is characterized by the metal layer comprising a copper foil, an electroless copper plating layer, and an electrolytic copper plating layer in the method for manufacturing a chip package (1).
In the method for manufacturing a chip package (2), the electroless copper plating layer and electrolytic copper plating layer can be formed in the through holes formed in the resin substrate before forming the Ni/Au film by electroplating, and the Ni/Au film can be also formed in the through holes by electroplating. As a result, the reliability of the chip package can be improved.
A method for manufacturing a chip package (3) according to the present invention is characterized by the metal layer comprising an electroless copper plating layer, or a copper foil and an electroless copper plating layer in the method for manufacturing a chip package (1).
In the method for manufacturing a chip package (3), by forming the electroless copper plating layer after forming the through holes in the resin substrate, the metal layer for the interconnection pattern and ball pads and the metal layer for the through holes can be formed at the same time, leading to the simplification of the chip package manufacturing process. The electroless copper plating layer can be formed to be thin, i.e. 1 micron or so. As a result, the subsequent etching of the electroless copper plating layer as a metal layer becomes easy. The quantity of overhang during the etching of the electroless copper plating layer can be made as small as possible. Therefore a high-density interconnection pattern can be easily achieved. When the metal layer comprises a copper foil and an electroless copper plating layer, the adhesive strength of the metal layer to the resin substrate can be increased in addition to the above effects.
A method for manufacturing a chip package (4) according to the present invention is characterized by including the step of conducting electroless plating and electroplating treatment of copper on the side walls of through holes after forming the through holes in the resin substrate; in one of the methods for manufacturing a chip package (1)-(3).
In the method for manufacturing a chip package (4), since a plating film of Cu which is a good conductor is formed on the side walls of the through holes before the Ni/Au plating treatment by electroplating, the Ni/Au plating film can be also formed on the side walls of the through holes by electroplating. As a result, the reliability of the chip package can be improved.
A method for manufacturing a chip package (5) according to the present invention is characterized by using a dry film resist having a principal constituent of an acrylic resin for forming the plating resist pattern in one of the methods for manufacturing a chip package (1)-(3).
The dry film resist having a principal constituent of an acrylic resin has high resistance to the Cu/Ni/Au plating solution and is favorably stripped by a release solution so that no residue of stripping is caused. Therefore, in the method for manufacturing a chip package (5), a precise interconnection pattern and ball pads can be formed. Therefore, the occurrence rate of shorting can be easily reduced.
A method for manufacturing a chip package (6) according to the present invention is characterized by using a liquid resist having a principal constituent of an acrylic resin for forming the plating resist pattern in one of the methods for manufacturing a chip package (1)-(3).
The liquid resist having a principal constituent of acrylic resin has excellent adhesiveness to the metal layer so that the pattern formation is precisely conducted, and has high resistance to the Cu/Ni/Au plating solution and is favorably stripped by a release solution so that no residue of stripping is caused. Therefore, in the method for manufacturing a chip package (6), a fine interconnection pattern and ball pads can be precisely formed. Therefore the occurrence rate of shorting can be easily reduced.
A method for manufacturing a chip package (7) according to the present invention is characterized by conducting cleaning treatment on the metal layer surface before forming the plating resist pattern in the method for manufacturing a chip package (5).
By conducting the cleaning treatment, the adhesiveness of the plating resist pattern to the metal layer surface is improved. As a result, the plating solution is prevented from penetrating under the plating resist pattern during electroplating so that the occurrence of shorting in the interconnection pattern can be inhibited.
A method for manufacturing a chip package (8) according to the present invention is characterized by conducting bake treatment on a plating resist and/or plating resist pattern before forming Ni and Au films by electroplating in one of the methods for manufacturing a chip package (1)-(3).
By the bake treatment, the optical setting reaction and/or thermosetting reaction of the plating resist is accelerated so that the adhesive strength thereof to the base metal layer is higher.
A method for manufacturing a chip package (9) according to the present invention is characterized by using an alkaline solution having a principal constituent of a copper ammine complex or tetraamminecopper (II) chloride as an etchant of the metal layer in the method for manufacturing a chip package (2).
The alkaline solution having a principal constituent of a copper ammine complex or a tetraamminecopper (II) chloride can etch only the Cu layer efficiently without dissolving the Ni and Au films. Therefore, the metal layer can be etched efficiently using the electroplating film of Ni/Au as an etching mask.
A method for manufacturing a chip package (10) according to the present invention is characterized by using a soft etching solution having a principal constituent of soda persulfate or mixture of hydrogen peroxide and sulfuric acid as an etchant of the metal layer, in the method for manufacturing a chip package (3).
The soft etching solution having a principal constituent of a soda persulfate or mixture of hydrogen peroxide and sulfuric acid can etch the Cu layer efficiently without dissolving the Au film. In addition, the soft etching solution is milder than the alkaline solution having a principal constituent of a copper ammine complex or a tetraamminecopper (II) chloride. Therefore, when the metal layer is an electroless copper plating layer, or a copper foil and an electroless copper plating layer with the electroplating film of Ni/Au used as an etching mask, the electroless copper plating layer, or the copper foil and electroless copper plating layer can be precisely etched efficiently with almost no overhang thereon.